multiprocessor architecture meaning in English

多处理机体系结构
多处理机系统结构

Examples

Backplanes bus specification for multiprocessor architectures : futurebus , logical layer specification
多处理机体系结构用底板总线规范:未来总线逻辑层规范
The proposed solution combined multiprocessor architecture and hierarchical operating system structure and could ensure that the system reliability in whole
接着,基于自行研制的实时操作系统ertos ,采用该设计方案构造了双机容错实现模型,并在予以实现。
Firstly , the dissertation expatiate the develop of epu ' s software and hardware . the hardware is a data acquisition system based on the ps multiprocessor architecture
硬件是以主从式多处理器结构为核心数据采集系统，主机和从机分别采用ti公司浮点dsp芯片7ms320c31pq和定点dsp芯片tms320f240 。
In aspect of hardware , the system used ps ( principal and sub - ordinate ) multiprocessor architecture . the master cpu 89c51 is used as the center of control and management , the slave cpu tms320f240 is used as the core part of data processing , dual port ram transfer data between two pieces of cpu
硬件部分延用传统的主从式系统硬件设计，以89c51为主机控制核心， tms320f206为从机核心，采用双口ram芯片解决主cpu与dsp之间的数据传输问题，配以适当的外围接口电路来完成各项功能。
Consequently , an urgent problem is to ensure the tolerance of hardware error , to strengthen the tolerance of software error , to integrate hardware and software fault - tolerant technique in operating system level . based on the above analysis , this thesis researches the techniques of reliability and multi - processors system and proposes a fault - tolerance real - time embedded multi - processor system based upon the loosely coupled multiprocessor architecture
在此基础上,本文对容错关键技术和多处理器系统进行了深入地研究,结合多处理器结构和现代操作系统的分层结构思想,提出了一种基于松耦合多处理器体系结构的实时嵌入式容错系统设计方案,以达到从整体上提高系统可靠性的目的。

multiprocessor architecture meaning in English

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